module LightPWM_Module
 #(
    parameter [3:0]  PWM_CYCLE_WIDTH = 4'd8  
 )
 (
    input               clk,
	 input               rstn,
    input               frame_clk,
	 output reg          light_mask,
	 
	 input  [PWM_CYCLE_WIDTH-1:0]       pwm_cycle,
	 input  [PWM_CYCLE_WIDTH-1:0]       duty_cycle
	 
	 
 );
 
   reg  [PWM_CYCLE_WIDTH-1:0]   cnt;
	//----------------------------------------------
	//--  描述：pwm计数
	//----------------------------------------------
   always@(posedge clk or negedge rstn)
   begin
	  if(rstn==1'b0)
	    cnt <= 'd0;
	  else 
       begin
		   if(cnt>=pwm_cycle)
			  cnt <= 'd0;
			else if((frame_clk)&&(cnt<pwm_cycle))
			  cnt <= cnt+1'b1;
		 end
   end
 
 	//----------------------------------------------
	//--  描述：输出light_mask
	//----------------------------------------------
   always@(posedge clk or negedge rstn)
   begin
	  if(rstn==1'b0)
	    light_mask <= 1'b0;
	  else 
       begin
         if((cnt<duty_cycle)&&(frame_clk))
			  light_mask <= 1'b1;
			else if(frame_clk)
			  light_mask <= 1'b0;
		 end
   end
 endmodule 